The power supply circuits used in this receiver include several important features. Three separate DC supplies are obtained via an autowound mains transformer which also carries a small isolated winding for the 6.3 volt CRT heaters.
The stabilized high current supply required by line, frame and sound output stages is provided by a novel circuit referred to in this article as the ‘Chopper’ supply. In this circuit a high power transistor is used to feed pulses of current at line frequency into an inductive reservoir which feeds the output load. The duration of the pulses is controlled by the demands of the load; increasing or decreasing as the load varies. A high degree of stabilization results, against mains and load variations, combined with a very low source impedance.
The chopper power supply is fed from a 200V point on the auto-transformer via rectifier W602 to give a 240V DC supply. The same point on the transformer is used with rectifier W601 to provide 240V DC for the video output transistors.
W603 and W604 are connected to form a full-wave rectifier centred on the neutral mains return. The rectified supply is fed through a series regulator VT6O1 which provides a 30V stabilized output. The base of the regulator is stabilized by a 30V zener W605.
The 30V stabilized supply is fed to the IF, Chrominance, Video, Line Oscillator, Beam Limiter, Frame Oscillator and Audio circuits. The UHF tuner 12V supply is also derived from this source. In addition, the chopper switching control circuit utilises this supply as a reference voltage.
This portion of the power supply provides the main current for the Line and Frame timebases and also drives the sound output stages.
The operation is as follows: Half-wave rectified DC is fed to the collector of the chopper transistor VT604 which is switched on and off at line frequency.The ON-OFF or mark-space ratio is continuously varied, accordingto the load requirements, by a feedback circuit which monitors the output voltage. The feedback loop effectively stabilizes the output voltage and simultaneously smoothes the 50 Hz ripple. Operational source impedance of the output is less than 1Ω. During the ON time the chopper transistor feeds high voltage energy into the reservoir inductance L603; at turn off, the feed end of the inductance is clamped to chassis potential by W616 and the stored energy flows into the load.
The trigger pulses for the chopper circuit are derived from the Line Oscillator which is powered by the 30V stabilized line. Therefore, the 30V supply must be fully established and the oscillator functioning at full amplitude before the chopper control circuit begins to operate.
The 240V DC from mains rectifier W602 is applied via high frequency choke L601 to collector of VT604. The switching control for the base is derived as follows:
A monostable multivibrator is formed by VT606, VT605 and VT603 (VT602 may be assumed to be fully conducting for the moment). Prior to the arrival of the Line Oscillator trigger pulse, VT606 and VT605 are ON and the phase of the windings in T602 is arranged so that chopper transistor VT604 is OFF.
When trigger pulses from the line timebase oscillator are applied to the base of VT603 the transistor is switched hard on, causing the collector to fall very close to chassis potential. C614 and C615, which were charged prior to trigger, are also lowered in potential which results in VT606 base being driven negative and VT605 turned off. The time period for which this pair are turned off is determined by the discharge time through R620 and the charged level of C614 and C615 before trigger. It follows, therefore, that by varying the charge on C615 a corresponding change will be produced in the mark-space ratio. This is accomplished by comparing the chopper output voltage with the 30V stabilized supply as follows:
VT608 monitors the output voltage of the chopper supply. Preset R629 (Set EHT) at the base sets the operating level. When the receiver is switched on, C623 is fully discharged, the Feedback Amplifier VT608 is off, and no charge is being fed back to C615; therefore, minimum mark-space ratio conditions apply and the chopper output voltage is low (1OV-15V). As C623 is slowly charged via R633, the feedback amplifier becomes operational, a charging voltage appears on the feedback loop and the mark-space ratio gradually opens up. This process continues until C623 reaches 30V, at which point W620 conducts and clamps the emitter circuit to the 30V line. The chopper output having now reached its preset operating voltage, a proportion of this voltage appears on the base of VT608 and is compared with the 30V stabilized supply at the emitter.
The transistor is now operating as a true invertor amplifier. Any variation in the chopper output voltage will therefore be amplified at the collector and fed back as a correction voltage to C615 which in turn will adjust the mark-space ratio.
C621 keeps the amplifier gain constant over the range of the preset control and R631 sets the upper limit of the voltage available in the adjustment range of R629 (Set EHT). To ensure that C623 discharges immediately the receiver is switched off or the mains supply interrupted, W619 and R633 are connected so that as soon as the interruption occurs, C623 is tied to the heavily loaded chopper supply output line which drops rapidly in potential. When the supply is restored, minimum mark-space conditions will apply until C623 is again fully charged thus avoiding momentary surges.
VT602 acts as a delay switch to ensure that the monostable remains inoperative until the 30V supply is established. Its base is driven from the 30V master zener W605. Once the zener conducts, VT602 is switched on.
This circuit gives extremely rapid protection to the Chopper transistor against transient overloads caused by flashover pulses, etc. Chopper transistor currentis continuously monitored through R610 which is connected in series with the switching decoupling capacitor C610. The voltage produced across the resistor is fed via W614 to cathode of SCR W622. The gate voltage, which determines the excess current level which will cause the SCR to fire, is adjusted by R622.
The anode of W622 is connected to the collector of chopper drive transistor VT605. When the SCR is fired, VT605 collector is taken down to chassis through W614, R611 and R610. The mark-space ratio will now be controlled by the trip circuit which will tend to limit the chopper base drive in proportion to the severity of the fault. An indication that the Dynamic Trip circuit is in operation is that the chopper output voltage, which is normally stable at some figure between 58V-65V, will drop below the 58V limit and fluctuate when the Brightness control is rotated. Frame foldover may be present. In the event of a persistent partial short which is not severe enough to blow the fuse or operate the Overload Cut-Out (when fitted), the receiver should be switched off as soon as possible.
Excess Voltage Trip
Should the chopper output voltage rise above 72V* caused by a short-circuit chopper transistor or faulty control circuit, etc., then zener W617 conducts and fires the ‘crowbar’ SCR W621, thus shorting the 240V line and operating the Cut-Out (when fitted) or blowing the main fuse.
*68V in some receivers,
Fuses and Cut-Out
In addition to the mains input fuse, the chopper output is fused at 2 amps and the 30V line at 500mA. Also in some chassis, a resettable Overload Cut-Outis fitted in the mains input.
General Circuit Notes
Two high frequency transistors are connected in grounded-base mode.Manually preset bias on the RF stage base permits adjustment for optimum performance in strong signal areas (RF Gain R5).
A three-section gang capacitor tunes the ¼-wave lecher lines to provide complete coverage of Bands IV and V. AFC is applied to the oscillator on all channels by van-cap diode W1 for optimum reset accuracy on colour reception.
The vision IF section comprises a four-stage broad-band amplifier with AGC on the first two stages VT1 01 and VT102.Response shaping is provided in the input circuit by bandpass coil L102; Sound rejector L101 adjusts the sound-vision carrier ratio, L103 is the adjacent channel sound rejector and transient correction is provided by L126. The single stage AFC discriminator and amplifier W104-W105 and VT107 is driven from the collector of the fourth stage VT104.
Two detector circuits are used:
W1O1 provides the sound and chrominance signals, and W102 is the luminance detector. A second sound rejector, L113 in the Luminance detector circuit, provides total sound-vision rejection of 36dB. Sound take-off is at the 6 MHz double tuned transformer L111-L112 feeding the two-stage amplifier VT108-VT109 which drives the sound discriminator. Audio is fed out via the Volume control to the Audio Amplifier on the Frame Timebase & Sound board.
The detected Luminance signal is applied to Luminance Delay Line Driver VT105, and the collector signal is fed out to the Luminance Delay Line on the Video board. The AGC Amplifier VT1O6 is driven from the emitter. Peak level AGC, working on the tips of the sync pulses, controls the gain of 1st and 2nd vision IF stages. Chrominance take-off is via a bandpass network, including L124-L125, to the ACC controlled Amplifier VT110. Constant amplitude Chrominance plus Burst is fed out to the Chrominance board.
The composite Chrominance signal is applied to the Chrominance and Burst channels. Burst channel is gated on by line pulses from VT308 which also drives chrominance blanking diodes W316-W317. Peak rectification of the amplified Burst by W301 provides ACC bias.
Amplified Burst is compared with the Reference Oscillator signal in Phase Discriminator L301-W302-W303 and appropriate correction applied to oscillator via DC Amplifier VT303. Oscillator carrier for the Demodulators is fed out from Emitter Follower VT305. VT306-VT307 and associated network generates the PAL switching waveform to drive switching diodes W309-W310 and to provide the ‘unkilling’ bias for the Chrominance Amplifier VT309.
The Chrominance signal minus Burst is amplified in VT309, gain controlled by R385 (Colour) and fed to Delay Line Driver VT310. The Delay Line and Matrix network yields the R—Y and B—Y signals which are then applied to the Demodulators. 90 degree oscillator phase shift is provided by L307 for the B—Y Demodulator. The demodulated signals are fed to the Video board.
The constant amplitude Luminance plus sync signal (8V p-p) is applied to the Post Luminance Delay Line Amplifier VT2O1, with manual amplitudecontrol by R207 (Contrast). Delay Line output is also fed to the Sync Separator VT203, and the composite sync is fed out to the timebases by Emitter Follower VT202.
After passing through VT2O1, the Luminance signal is applied to the base of the Luminance Driver VT206. Brightness and Beam Limiter control is applied at this point from Offset Pulse Generator and Adder circuit VT204 and VT205.
The effect of this circuit is to allow positive or negative displacement of the picture information relative to the sync pulses and porches by operation of the Brightness control or the Beam Limiter circuit. The composite signal is referred to as ‘offset luminance’.
After passing through the Luminance Driver VT206, the offset luminance signal is applied simultaneously at the bases of the Red, Green and Blue Video Output stages.
The colour difference signals are amplified in three separate channels (G-Y being derived from the other two by a matrix circuit) and applied via preset gain controls to the emitters of the appropriate output stages.
The back porches of the colour output signals are stabilized at a fixed DC level by clamping pulses applied at the three collectors via R246, R247 and R248. R.G.B drive is then applied to the cathodes of the CRT.
FRAME TIMEBASE AND SOUND
A multivibrator oscillator is formed by VT421-VT422 with sync injected via integrator R421-C421 and filter diode W421.Frame Timebase The drive waveform is applied via emitter follower VT423 to output stage VT424. Emitter resistor R440 is returned to a point which is at 1 .6V relative to chassis, this being the voltage across bias diodes W424-W425. This sets the correct bias conditions for the output stage to be cut off during flyback.
Two linearity adjustments are provided, and the ‘sit-up’ preset R434 is adjusted to obtain the correct conditions at start of scan. The positive-going pulse from the output collector is fed to VT425 which conducts heavily during flyback and provides a frame flyback suppression pulse at its collector. Line suppression pulses are fed in through R448 and C434 and the combined suppression pulses are taken to the CR1 grid via C435 and R453. DC return for the grid is the slider of R450 which is connected in a potentiometer chain between the 200V clamp voltage obtained from the Video board and the -850V supply from the Line Timebase. This ensures that grid to cathode potentials are unaffected by fluctuations in the supply voltage.
The detected signals from the IF board are fed via Volume control R406 to the 1st audio stage VT4O1. Direct coupling is employed to Driver stage VT402 which feeds the Class B complementary output stage VT403-VT404. DC conditions are stabilized by negative feedback via R409, with C406 and R41 0 included for correct frequency response.
LINE TIMEBASE AND BEAM LIMITER
W501-W502 form a conventional flywheel phase discriminator operating from negative sync pulses fed in via R503 and a reference sawtooth from winding BC on the EHT transformer T503. Line Timebase Output from the phase discriminator is fed via suitable filter networks to the base of the control stage VT5O1 VT5O1 forms a series reactance circuit which controls the oscillator frequency by means of a variable DC voltage. The 90 degree voltage lag in the collector means that the transistor behaves as a variable capacitor. VT502 is connected as a Hartley over coupled type oscillator with the necessary voltage phase difference between base and collector obtained by tapped coil L501. The oscillator is energised by the 30V stabilized supply and the trigger pulses for the Chopper Power Supply are taken from the collector.
The square waves appearing at the collector are transformer fed to the Driver stage VT503. The series connected output transistors are parallel driven at the bases and W504 operates as the efficiency diode. Two jellypot transformers are used: T504 produces the line scan, and T503 provides the 8kV pulse for the EHT tripler. Linearity adjustment is provided by correction coil L503. The sawtooth appearing in winding BC of T504 is rectified to provide Horizontal Shift potential. Rectifier W505 provides 1000V DC for the network feeding the Al tube electrodes. Focus potential is obtained from a potentiometer chain which is connected in shunt with the EHT.
Beam Limiter Circuit
The brightness and beam limiter bias which is applied to the Video board via 2/22 is negative-going for increasing brightness. The Beam Limiter circuit monitors a current which is proportional to the total EHT beam current by means of the resistor R907 which is connected in the return side of the line scan and EHT circuits. When the beam current exceeds the permitted maximum, the voltage across R907 rises to a level at which the collector current of VT9O1 decreases thus causing an increase in collector voltage. This in turn alters the brightness and beam limiter bias in the positive-going direction to reduce the CRT cathode current.
In addition to the dynamic convergence networks, the Convergence board also carries the Al potential networks and Vertical Shift adjustment. In the frame convergence circuit, R.G. Symmetry R71 2 is in parallel with the series connected scan coils. DC return for the scan coils is via the Vertical Shift R7l 5 to the HT supply. C705 isolates the convergence network from the supply. The waveform applied to the Blue Amp and R.G. Amp presets is a sawtooth modified by a large parabolic component caused by integration in C706. The Blue Tilt and R.G. Tilt presets receive a mainly sawtooth voltage. W705 is a DC clamp.
The line convergence network is connected at the earthy ends of the parallel connected line scan coils. sawtooth voltage developed across R707-R708 is applied in parallel to the R.G. and Blue networks. In the R.G. network W701 conducts in the negative half of the scan and the current builds up in the convergence coils in a parabolic manner from zero to a peak value determined by the R.G. Amp (R702). During flyback W701 is turned off and the current in the convergence coils decays through W702 and the Tilt network.