Because no thermionic valves will be employed in the line store, the intent of this topic is to keep the line stores separate from the valve converter project. I intend to use ready made units rather try to attempt to develop entirely new line store units. The choice will be between the simple FiFo chip solution using the Dallas DS2010 or the rather complex S-RAM line store. I'm receptive to any new ideas.
Also, can the 64uS glass delay line be adapted to function on a baseband video waveform? In a PAL decoder the delay line processes the 4.43Mhz chroma signal.
The attachments show the S-RAM line store unit and it's control PCB. Designed in 1985. Modified in 1989 to employ Cypress CY7C128 memories.
Till Eulenspiegel.
Extract from the 1966 Philips Technical Review. Volume 29, page 250. Performance of the delay line at 25degrees C.
Phase-delay tolerance Bandwidth (3 dB): {lower limit upper limit Insertion loss (at 4.43 MHz) Terrninating resistances Attenuation of 3, reflections Attenuation of other reflections
± 5 ns < 3.43 MHz > 5.23 MHz 10 ± 3 dB 150 ohms > 21 dB > 26 dB.
So it follows the glass delay line will not handle a full video waveform, that is DC to 5.5Mhz.
Till Eulenspiegel.
That would make sense as there would be no reason to design it for the full bandwidth. I do have in my mind a mental image of an early colour set with a coaxial cable delay line, looped up on the side of the cabinet and wondered if it might have been an early SECAM decoder.
However, before taking the velocity of propagation of the coax (~80%) into account, 1μS = 300m in free air, so that would be an awfully long piece of coax for 64μS!
It must have been an early luminance delay line that I was remembering!
When all else fails, read the instructions
So it follows the glass delay line will not handle a full video waveform, that is DC to 5.5Mhz.
Till Eulenspiegel.
That's because they were never intended to do so, and also they are not 64us long - they are 63.943us long.
That would make sense as there would be no reason to design it for the full bandwidth. I do have in my mind a mental image of an early colour set with a coaxial cable delay line, looped up on the side of the cabinet and wondered if it might have been an early SECAM decoder.
However, before taking the velocity of propagation of the coax (~80%) into account, 1μS = 300m in free air, so that would be an awfully long piece of coax for 64μS!
It must have been an early luminance delay line that I was remembering!
Typical propagation delay for coax is 0.67 - I have a table that lists these in the handbook for my TDR. A piece of triaxial cable for TV cameras is usually 0.67 between inner shield and core, but about 0.78 between the shields - this is due to the different dielectrics amongst other reasons.
We always allowed 5ns/metre for PSF1/3.
The attachment shows the simple line store standards converter that was designed in 1985.
The verboard card carries a divide by 405 counter and is a recent addition, that is if one considers five years ago as recent. The 405 sync and timing board generates the mixed syncs for the output standard. However, the eight broad pulses are initiated by the 625 frame sync pulse. This pulse opens the 2H pulse gate which enables 28 pulses to pass, eight of those pulses trigger the 40microsecond timer, (actually a 555) the broad pulse gate is reset on the ninth 2H pulse. The broad pulses are inserted into the sync pulse chain. The reason for counting 28 2H pulses is to generate the 1400uS frame blanking pulse. So it follows in the absence of a 625 input signal no broad pulses will be generated and a continuous stream of line pulses will be the result. The verocard has a divide by 405 counter which will produce a dummy frame sync trigger when no 625 signal is available.
Till Eulenspiegel.
The standards converter was tried out yesterday, needless to say it doesn't work.
For starters the thirty-three old switched model power supply will need recapping. the main 5 volt supply is well down, it's delivering only 4.3 volts. The +12V and -12V supplies are about right.
The attachment shows the underside of the converter. The modulator is the original David Looser design that appeared in the August 1984 Television magazine.
Till Eulenspiegel.
Two CA3306 ADC chips are employed to realise 7bits wide digitised video. It is possible to get away with a single CA3306 to realise six bit video but the effect of map contours will be noticeable on shaded areas of the picture. Only the active part of the video waveform is digitised, no point digitising the sync pulses.
The line stores will support eight bit digitised video.
Seems that no clock pulses are present at pin 7 of the CA3306 ADCs.
The attachment gives details of the RCA CA3300. First deliveries of this device was in 1983. Now replaced by the CA3306. An SMD version is available, type HI1172.
Till Eulenspiegel
I am watching the thread with lots of interest, must admit though it’s beyound my capabilities.
Frank
Hi Frank, in 1984 I knew absolutely nothing about TV standards converters. I was aware such things existed because we all knew that the 405 line pictures originated from the 625 line standard and had done so since the mid sixties. Did consider optical conversion, nothing more than a 405 camera pointing at a 625 monitor. In fact that's how the very first converters worked. First application of an optical converter was the exchange of programs between England and France. 1952?
Till Eulenspiegel.
The missing ADC clock pulse was traced to a bad solder connection to the wire test link close to the 74LS04 hex inverter IC. This IC serves to invert and delay the application of clock pulses to the ADC. Although the 625 clock frequency is only 10.125Mhz things like propagation delays in chips has to be considered, for example the correct timing between the data issuing from the ADC and the line store address counters is achieved.
625 clock frequency is 10,125Mhz = 648 X 15,625Khz. 405 clock frequency is 6.561Mhz =648 X 10.125Khz.
Till Eulenspiegel.
Attachment shows the input 625 video and the converted 405 waveform. The 4.433Mhz chroma signal has to be filtered out before it reaches the ADC because it causes patterning to the converted video. 'Scope was synchronised to the 625 frame sync pulse and set to the delay function so that individual lines can be selected and observed.
Till Eulenspiegel.
625 clock frequency is 10,125Mhz = 648 X 15,625Khz. 405 clock frequency is 6.561Mhz =648 X 10.125Khz.
The multiplier 648, I presume it’s not arbitrary but how is that number arrived at?
Frank
Hi Frank, that's right the clock pulse frequency of 10.125Hhz is not an arbitrary figure. The first 74LS161 counter divides the 10.125meg clocks by 4 down to 2.531250Mhz, this is the frequency chosen for the line store timing and switching counters. By employing two 74LS161 counter ICs further division takes place, by 162 to produce the 15,625Hz comparison signal for the clock oscillator phase lock loop. The 2.531250Mhz pulse train is divided by 250 (two 74LS161 counters) to produce the 10,125Hz reference for the 6.561Mhz 405 clock pulse oscillator. An exact 81/125 relationship exits between the two line standards, essential if perfect interlace is to be maintained on 405 lines. So it follows that there are 648 samples per complete 64uS line period. However, only the active video part is supplied to the line stores which is 52uS in the 625 system. The active video part consists of 526 samples. Actually, if the 625 clock frequency was 10MHz the active part of the video signal would be a very convenient 512 samples over 52uS.
The clock frequency of 10,125Mhz is a bit on the low side and an alternative figure of 12,656250Mhz might be considered for a later converter project, 625 lines = 15,625Hz X 810. 405 clocks = 8.201250Mhz.
Till Eulenspiegel.
Thanks for the explanation, yes I was wondering about the 10,125Mhz clock speed being a bit low, from memory, Nyquist rate would be at least twice the max frequency to be converted.
Not that my maths is good enough for Fourier transforms and all the rest that’s involved.
Frank
Hi Frank, 10.125Mhz is the lowest clock frequency one can get away with and is slightly below 2X the maximum video frequency on 625 lines. But it has to be taken into consideration that the 4.43Mhz chroma signal has to be notched out so in reality roll off starts about 4Mhz. Also the low(ish) clock frequency is a legacy from my first attempts at constructing a 625/405 converter late in 1984. The design of the converter has hardly changed since then. It also has to borne in mind the 1980s was the busiest decade in the shop so in reality there wasn't really much spare time for projects like the converter.
Till Eulenspiegel.
The standards converter is inputted from a 625 line test card generator. The close up picture of the frequency gratings show that the converter can resolve the 2.5Mhz bars but as expected there is no trace of activity of the 3Mhz bars. The other picture shows the effect of having no interpolation of the 220 dropped lines. The effect is made all the worse because of picture Interlacing. The dropped lines are organised in pairs thus making the converted picture look even worse.
Till Eulenspiegel.
